Моделиране и симулиране на микропроцесор с RISC архитектура
Modeling and Simulation of a Microprocessor with RISC Architecture

Summary/Abstract: This report examines the modeling of a microprocessor based on the principles of RISC architecture. This architecture is characterized by a simplified instruction set, a fixed instruction format, and efficient use of a register file. A microprocessor with this architecture enables optimized pipelined instruction execution and high performance with low hardware complexity. For modeling and simulation of the RISC-based microprocessor, the VHDL hardware description language was used. The modeling of the main blocks of the RISC architecture is presented. The ISE Project Navigator environment was used to validate the developed model.

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