Hardware Design Automation with Python and Verilog HDL
Hardware Design Automation with Python and Verilog HDL

Summary/Abstract: This article discusses an approach to facilitate the design of digital devices of increasing complexity by using the Python language. In this way, both synthesizable designs and non-synthesizable testbench modules can be created. Some practical examples used in the training of students are considered, including the design of a series of frames for control of matrix indicator, a binary multiplier, implemented both as a memory and by using a recursive algorithm. The capabilities of programming languages are increasingly used to create verification environments, as they provide convenience in describing the behavior in the submission of test vectors and making comparisons with the expected response despite the requirement for parallelism in the design. Also, in the verification process, the need for low-level hardware knowledge is not as great as when creating synthesizable designs. In this sense, the software approach, including the concept of object-oriented programming, turns out to be very appropriate. This makes working with complex designs more accessible, particularly for university students, saving them time and allowing them to concentrate on tasks with a higher level of difficulty.

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